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74LVX161284A Low Voltage IEEE 161284 Translating Transceiver
June 1999 Revised July 2000
74LVX161284A Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284A contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard, with the exception of output slew rate, and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive ( 14 mA) and are connected to a separate power supply pin (VCCcable) to allow these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCCcable supply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1-A8/B1-B8 transceiver pins.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals with the exception of output slew rate s Translation capability allows outputs on the cable side to interface with 5V signals s All inputs have hysteresis to provide noise margin s B and Y output resistance optimized to drive external cable s B and Y outputs in high impedance mode during power down s Inputs and outputs on cable side have internal pull-up resistors s Flow-through pin configuration allows easy interface between the "Peripheral and Host" s Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Order Number 74LVX161284AMTD Package Number MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names HD DIR A1-A8 B1-B8 A9-A13 Y9-Y13 A14-A17 C14-C17 PLHIN PLH HLHIN HLH Description High Drive Enable Input (Active HIGH) Direction Control Input Inputs or Outputs Inputs or Outputs Inputs Outputs Outputs Inputs Peripheral Logic HIGH Input Peripheral Logic HIGH Output Host Logic HIGH Input Host Logic HIGH Output
(c) 2000 Fairchild Semiconductor Corporation
DS500204
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74LVX161284A
Logic Symbol
Truth Table
Inputs DIR L HD L B1-B8 Data to A1-A8, and A9-A13 Data to Y9-Y13 (Note 1) C14-C17 Data to A14-A17 PLH Open Drain Mode L H B1-B8 Data to A1-A8, and A9-A13 Data to Y9-Y13 C14-C17 Data to A14-A17 H L A1-A8 Data to B1-B8 (Note 2) A9-A13 Data to Y9-Y13 (Note 1) C14-C17 Data to A14-A17 PLH Open Drain Mode H H A1-A8 Data to B1-B8 A9-A13 Data to Y9-Y13 C14-C17 Data to A14-A17
Note 1: Y9-Y13 Open Drain Outputs Note 2: B1-B8 Open Drain Outputs
Outputs
Logic Diagram
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74LVX161284A
Absolute Maximum Ratings(Note 3)
Supply Voltage VCC VCC--Cable VCC--Cable Must Be VCC Input Voltage (VI)--(Note 4) A1-A13, PLHIN , DIR, HD B1-B8, C14-C17, HLHIN B1-B8, C14-C17, HLHIN Output Voltage (VO) A1-A8, A14-A17, HLH B1-B8, Y9-Y13, PLH B1-B8, Y9-Y13, PLH DC Output Current (IO) A1-A8, HLH B1-B8, Y9-Y13 PLH (Output LOW) PLH (Output HIGH) Input Diode Current (IIK)--(Note 4) DIR, HD, A9-A13, PLH, HLH, C14-C17 Output Diode Current (IOK) A1-A8, A14-A17, HLH B1-B8, Y9-Y13, PLH DC Continuous VCC or Ground Current Storage Temperature ESD (HBM) Last Passing Voltage
Recommended Operating Conditions
Supply Voltage VCC VCC--Cable DC Input Voltage (VI) Open Drain Voltage (VO) Operating Temperature (TA) 3.0V to 3.6V 3.0V to 5.5V 0V to VCC 0V to 5.5V
-0.5V to +4.6V -0.5V to +7.0V
-0.5V to VCC + 0.5V -0.5V to +5.5V (DC) -2.0V to +7.0V*
*40 ns Transient
-40C to +85C
-0.5V to VCC +0.5V -0.5V to +5.5V (DC) -2.0V to +7.0V*
*40 ns Transient
25 mA 50 mA
84 mA
-50 mA -20 mA 50 mA -50 mA 200 mA -65C to +150C
2000V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIK VIH Input Clamp Diode Voltage Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VT Minimum Input Hysteresis VOH Minimum HIGH Level Output Voltage Bn, Yn Bn, Yn PLH An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, Bn, PLHIN, DIR, HD Cn HLHIN An, HLH Parameter VCC (V) 3.0 3.0-3.6 3.0-3.6 3.0-3.6 3.0-3.6 3.0-3.6 3.0-3.6 3.3 3.3 3.3 3.0 3.0 3.0 3.0 3.15 VCC--Cable TA = -40C to +85C (V) 3.0 3.0-5.5 3.0-5.5 3.0-5.5 3.0-5.5 3.0-5.5 3.0-5.5 5.0 5.0 5.0 3.0 3.0 3.0 4.5 3.15 Guaranteed Limits -1.2 2.0 2.3 2.6 0.8 0.8 1.6 0.4 0.8 0.2 2.8 2.4 2.0 2.23 3.1 V V VT+-VT- VT+-VT- VT+-VT- IOH = -50 A IOH = -4 mA IOH = -14 mA IOH = -14 mA IOH = -500 A V V Units V Conditions Ii = -18 mA
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74LVX161284A
DC Electrical Characteristics
Symbol VOL Maximum LOW Level Output Voltage Bn, Yn Bn, Yn PLH PLH RD Maximum Output Impedance Minimum Output Impedance RP Maximum Pull-Up Resistance Minimum Pull-Up Resistance IIH Maximum Input Current in HIGH State IIL Maximum Input Current in LOW State IOZH Maximum Output Disable Current (HIGH) IOZL Maximum Output Disable Current (LOW) IOFF IOFF IOFF--ICC IOFF--ICC2 ICC Power Down Output Leakage Power Down Input Leakage PowerDown Leakage to VCC Power Down Leakage to VCC--Cable Maximum Supply Current B1-B8, Y9-Y13, C14-C17 B1-B8, Y9-Y13 C14-C17 A9-A13, PLHIN, HD, DIR, HLHIN C14-C17 C14-C17 A9-A13, PLHIN, HD, DIR, HLHIN C14-C17 C14-C17 A1-A8 B1-B8 B1-B8 A1-A8 B1-B8 B1-B8 B1-B8, Y9-Y13, PLH C14-C17, HLHIN B1-B8, Y9-Y13 B1-B8, Y9-Y13 Parameter An, HLH
(Continued)
VCC (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.0 0.0 0.0 0.0 3.6 3.6 VCC--Cable TA = -40C to +85C (V) 3.0 3.0 3.0 4.5 3.0 4.5 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.6 3.6 5.5 3.6 3.6 5.5 3.6 3.6 5.5 3.6 3.6 5.5 0.0 0.0 0.0 0.0 3.6 5.5 Guaranteed Limits 0.2 0.4 0.8 0.77 0.95 0.9 60 55 30 35 1650 1650 1150 1150 1.0 50.0 100 -1.0 -3.5 -5.0 20 50 100 -20 -3.5 -5.0 100 100 250 250 45 70 A mA mA A A A A mA mA A A A A mA VO = 5.5V VI = 5.5V (Note 6) (Note 6) VI = VCC or GND VI = VCC or GND A VI = 3.6V VI = 3.6V VI = 5.5V VI = 0.0V VI = 0.0V VI = 0.0V VO = 3.6V VO = 3.6V VO = 5.5V VO = 0.0V (Note 5)(Note 7) V IOL = 50 A IOL = 4 mA IOL = 14 mA IOL = 14 mA IOL = 84 mA IOL = 84 mA (Note 5)(Note 7)
Units
Conditions
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD = HIGH). Note 6: Power-down leakage to VCC or VCC--Cable is tested by simultaneously forcing all pins on the cable-side (B1-B8, Y9-Y13, PLH, C14-C17 and HLHIN) to 5.5V and measuring the resulting ICC or ICC--Cable. Note 7: This parameter is guaranteed but not tested, characterized only.
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74LVX161284A
AC Electrical Characteristics
TA = -40C to + 85C Symbol Parameter VCC = 3.0V-3.6V VCC--Cable = 4.5V-5.5V Min tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tSKEW tPHL tPLH tPHL tPLH tPHZ tPLZ tPZH tPZL tPHZ tPLZ tpEN tpDIS A1-A8 to B1-B8 A1-A8 to B1-B8 B1-B8 to A1-A8 B1-B8 to A1-A8 A9-A13 to Y9-Y13 A9-A13 to Y9-Y13 C14-C17 to A14-A 17 C14-C17 to A14-A 17 LH-LH or HL-HL PLHIN to PLH PLHIN to PLH HLHIN to HLH HLHIN to HLH Output Disable Time DIR to A1-A8 Output Enable Time DIR to A1-A8 Output Disable Time DIR to B1-B8 Output Enable Time HD to B1-B8, Y9-Y13 Output Disable Time HD to B1-B8, Y9-Y13
(i) A1-A8 to B1-B8, A9-A13 to Y9-Y13 (ii) B1-B8 to A1-A8 (iii) C14-C17 to A14-A17
Units
Figure Number
Max 8.5 8.5 14.0 14.0 8.5 8.5 10.0 10.0 2.0 8.5 8.5 10.0 12.0 10.0 10.0 10.0 10.0 13.0 10.0 8.0 12.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1 Figure 2 Figure 3 Figure 3 Figure 1 Figure 2 Figure 3 Figure 3 (Note 8) Figure 1 Figure 2 Figure 3 Figure 3 Figure 4 Figure 5 Figure 6 Figure 2 Figure 2
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
Note 8: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type:
Capacitance
Symbol CIN CI/O (Note 9) Parameter Input Capacitance I/O Pin Capacitance Typ 3 5 Units pF pF VCC = 3.3V Conditions VCC = 0.0V (HD, DIR, A9-A13, C14-C17, PLHIN and HLHIN)
Note 9: CI/O is measured at frequency = 1 MHz, per MIL-STD-883B, Method 3012
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74LVX161284A
AC Loading and Waveforms
Pulse Generator for all pulses: Rate 1.0 MHz; ZO 50; tf 2.5 ns, tr 2.5 ns.
FIGURE 1. tPHL Test Load and Waveforms A1-A8 to B1-B8 A9-A13 to Y9-Y13 PLHin to PLH
FIGURE 2. tPLH, tpEn, tpDis Test Load and Waveforms A1-A8 to B1-B8, A9-A13 to Y9-Y13 PLHin to PLH, HD to B1-B8, Y9-Y13, PLH
VMO = 50% VCC
FIGURE 3. tPHL, tPLH Test Load and Waveforms B1-B8 to A1-A8, C14-C17 to A14-A17, HLHin to HLH
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74LVX161284A
AC Loading and Waveforms
(Continued)
FIGURE 4. tPHZ and tPLZ Test Load and Waveforms, DIR to A1-A8
FIGURE 5. tPZH and tPZL Test Load and Waveforms, DIR to A1-A8
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74LVX161284A
AC Loading and Waveforms
(Continued)
FIGURE 6. tPHZ and tPLZ Test Load and Waveforms DIR to B1-B8
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74LVX161284A Low Voltage IEEE 161284 Translating Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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